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? e94612b5z-te us audio multiplexing decoder CXA1734S 30 pin sdip (plastic) absolute maximum ratings (ta=25?) supply voltage v cc 11 v operating temperature topr ?0 to +75 ? storage temperature tstg ?5 to +150 ? allowable power dissipation p d 1.35 w range of operating supply voltage 9 0.5 v applications tv, vcr and other decoding systems for us audio multiplexing tv broadcasting structure bipolar silicon monolithic ic description the CXA1734S is an ic designed as a decoder for the zenith tv multi-channel system also corresponds with i 2 c bus. functions include stereo demodulation, sap (separate audio program) demodulation and dbx noise reduction. various kinds of filters are built in while adjustment and mode control are all executed through i 2 c bus. features audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. almost any sort of signal processing is possible through this ic. all adjustments are possible through i 2 c bus to allow for automatic adjustment. various built-in filter circuits greatly reduce external parts. standard i/o level input level compin (pin 11) 245 mvrms output level lout (pin 29) 490 mvrms rout (pin 28) 490 mvrms pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 25 24 26 27 28 29 30 nc lout rout itime vcatc vcawgt veout vetc vewgt ve sapout gnd noisetc vcain sapin sda scl dgnd sad vgr iref mainin plint stfil compin saptc subout stin v cc mainout sony reserves the right to change products and specifications without prior notice. this information does not convey any license by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustrating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits.
? CXA1734S block diagram 8 13 28 29 5 6 4 3 2 1 18 19 14 27 12 16 17 15 11 20 21 22 23 24 25 26 7 9 10 vgr iref sad dgnd scl sda sapout sapin stin ve vewgt vetc veout vcain vcawgt vcatc rout mainin mainout subout plint stfil compin v cc gnd noisetc saptc itime lout ire f sw lpf lpf hpf rmsdet rmsdet vca ve deem logic matrix vca lpf lpf 1/2 1/4 vco lflt stlpf "stlpf" vca lpf bpf sapvco lpf noise det sapind sapfdet "ponres" stind "saplpf" sapvdet "sap" "noise" att stvco sapvco stlpf saplpf nrsw/fomo/sapc/m1 wideband spectral "stereo" deem flt "sapvco" amp (+4db) i c bus i/f 2 +6db
? CXA1734S pin symbol pin equivalent circuit description no. voltage pin description (ta = 25?, v cc = 9 v) 1 2 3 4 5 sda scl dgnd sad vgr 1.3v serial data i/o pin. v ih > 3.0 v v il < 1.5 v serial clock input pin. v ih > 3.0 v v il < 1.5 v digital block gnd. slave address control switch. the slave address is selected by changing the voltage applied to this pin. band gap reference output pin. connect a 10 ? capacitor between this pin and gnd. 1 7.5k 4.5k 5 4k 3k 7.5k v cc 35 2.1v 2 2 7.5k 35 2.1v 19.5k 4 4k 3k v cc 2v 40k 80k 10k v cc 4 4 11k 9.7k 19.4k 2.06k 3k 147 5 v cc 1.3v 11k 11k 3
? CXA1734S pin symbol pin equivalent circuit description no. voltage 6 7 8 9 iref mainin mainout plint 1.3v 4.0v 4.0v 6.3v set the filter and vco reference current. the reference current is adjusted with the bus data based on the current which flows to this pin. (connect a 62 k ?%) resistor between this pin and gnd.) input the (l + r) signal from mainout (pin 8). (l + r) signal output pin. pilot cancel circuit loop filter integrating pin. (connect a 1 ? capacitor between this pin and gnd.) 40k 40k 30k 30p 1.8k 16k 6.3k 147 30k 15k 30k v cc 6 2 v cc 147 23k 23k 47k 4v v cc 10 7 v cc 147 1k 15k 8 v cc 4 200 v cc 147 12k 12k 9 10k 20k 20k 20k 26 50
? CXA1734S pin symbol pin equivalent circuit description no. voltage 10 11 12 13 stfil compin saptc subout 5.3v 4.0v 4.5v 4.0v stereo block pll loop filter integrating pin. audio multiplexing signal input pin. set the time constant for the sap carrier detection circuit. (connect a 4.7 ? capacitor between this pin and gnd.) (l - r) signal output pin. v cc 147 3k 3k 150k 4k 1k 4k 75k 75k 12k 1k 10 v cc 147 50k 3k 4k 4k 16k 4k 20k 3v 11 24k 22k 8k 4k 3k 10 k v cc 1k v cc 50 12 2k 2k 2k 4k 1k 147 500 14.4k 500 13 4k 10p 2k 2k vcc
? CXA1734S pin symbol pin equivalent circuit description no. voltage 14 19 15 16 17 18 20 stin sapin v cc noisetc gnd sapout ve 4.0v 4.0v 3.0v 4.0v 4.0v input the (l - r) signal from subout (pin 13). input the (sap) signal from sapout (pin 18). supply voltage pin. set the time constant for the noise detection circuit. (connect a 4.7 ? capacitor and a 200 k resistor between this pin and gnd.) analog block gnd. sap fm detector output pin. variable de-emphasis integrating pin. (connect a 2700 pf capacitor and a 3.3 k resistor in series between this pin and gnd.) 23k 147 47k 20k 11.7k 23k 4v 14 19 147 47k 4v 3k 3k 3.3k 4k 4v vcc 8k 2 16 10k 1k 2k vcc 15 17 24k 500 vcc 18 5p 500 4k 17k 4v 7.4k 147 10 50 7.5k 147 20
? CXA1734S pin symbol pin equivalent circuit description no. voltage 21 22 23 24 vewgt vetc veout vcain 4.0v 1.7v 4.0v 4.0v weight the variable de- emphasis control effective value detection circuit. (connect a 0.047 ? capacitor and a 3 k resistor in series between this pin and gnd.) determine the restoration time constant of the variable de-emphasis control effective value detection circuit. the specified restoration time constant can be obtained by connecting a 3.3 ? capacitor between this pin and gnd. variable de-emphasis output pin. (connect a 4.7 ? non- polar capacitor between pins 23 and 24.) vca input pin. input the variable de- emphasis output signal from pin 23 via a coupling capacitor. 21 vcc 4v 36k 2.9v 500 147 500 8k 30k 8 4k 50 20k 4v vcc 4 22 4 50 7.5 vcc 10k 500 23 500 5p v cc 20k v cc 24 47k 47k
? CXA1734S pin symbol pin equivalent circuit description no. voltage 25 26 27 vcawgt vcatc itime 4.0v 1.7v 1.3v weight the vca control effective value detection circuit. (connect a 1 ? capacitor and a 3.9 k resistor in series between this pin and gnd.) determine the restoration time constant of the vca control effective value detection circuit. the specified restoration time constant can be obtained by connecting a 10 ? capacitor between this pin and gnd. set the reference current for the effective value detection timing current. the reference current is adjusted with the bus data ?pectral?based on the current which flows to this pin. the timing current determines the restoration time constant of the detection circuit and the variable de-emphasis characteristics. connect a 43 k (?%) resistor between this pin and gnd. 4k v cc 25 30k 8k 36k 2.9v 3p 500 500 147 40k 40k 50 8 26 v cc 4k 20k 4 4 50 7.5 40k 40k 30k 30p 1.8k 2.6v 25k 147 20k 40k 10k 27 v cc 47k 4
? CXA1734S pin symbol pin equivalent circuit description no. voltage 28 29 30 rout lout nc 4.0v right channel output pin. left channel output pin. 3p 3k 500 28 29 500 v cc 15k 30
?0 CXA1734S electrical characteristics main (l+r) =245mvrms (pre-emphasis : off) compin input level sub (l-r) =490mvrms (dbx-tv : off) (100% modulation level) pilot =49mvrms sap carrier =147mvrms f h =15.734khz no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 item current consumption main output level de-emphasis frequency characteristics main lpf frequency characteristics main distortion main overload distortion mono s/n sub output level sub lpf frequency characteristics sub distortion sub overload distortion sub s/n sub pilot leak st on level st on/off hysteresis symbol icc vmain fcdeem fcmain thdm thdmmax snmain vsub fcsub thdsub thdsmax snsub pcsub thst hyst mode mono mono mono mono mono mono st st st st st st st st input 11 11 11 11 11 11 11 11 11 11 11 11 11 11 min. 22 440 ?.2 ?.0 61 150 ?.0 56 ?.0 3.5 typ. 32 490 0 ?.0 0.1 0.15 69 190 ?.5 0.1 0.5 64 1.0 ?.0 6.0 max. 42 540 1.0 1.0 0.5 0.5 230 1.0 1.0 2.0 7.0 ?.0 8.5 unit ma mvrms db % db mvrms db % db mvrms db input signal main 1k 100% pre-em on main 5k 30% pre-em on main 12k 30% pre-em on main 1k 100% pre-em on main 1k 200% pre-em on no signal sub 1k 100% nr-off sub 12k 30% nr-off sub 1k 100% nr-off sub 1k 200% nr-off f h 0db (49mvrms) f h 0db (49mvrms) f h f h output 28 29 28 29 28 29 28 29 28 29 28 29 13 13 13 13 13 13 others using 15 khz lpf using 15 khz lpf using 15 khz lpf using 15 khz lpf compared with the test2 output level using 15 khz lpf using 15 khz lpf using 15 khz lpf using 15 khz lpf compared with the test8 output level using f h bpf 0db=49mvrms 0db=49mvrms conditions
?1 CXA1734S no. 16 17 18 19 20 21 22 23 item st separation 1 st separation 2 sap output level sap lpf frequency characteristics sap distortion sap s/n sap on level sap on/off hysteresis symbol stsep1 stsep2 vsap fcsap thdsap snsap thsap hysap mode st st sap sap sap sap sap sap input 11 11 11 11 11 11 11 11 min. 23 23 150 ?.0 46 ?2 2.5 typ. 35 35 190 0 2.5 56 ? 4 max. 230 2.5 6.0 ?.5 5.5 unit db mvrms db % db input signal st 300hz 30%, nr-on st 3khz 30%, nr-on sap 1k 100% nr-off sap 10k 30% nr-off sap 1k 100% nr-off sap carrier 147mvrms sap carrier sap carrier output 28 29 28 29 18 18 18 18 others l ? r r ? l l ? r r ? l using 15khz lpf using 15khz lpf using 15khz lpf compared with the test18 output level 0db=147mvrms 0db=147mvrms conditions
?2 CXA1734S i 2 c bus block items (sda, scl) i 2 c bus load conditions: pull-up resistor 4 k (connect to +5 v) load capacity 200 pf (connect to gnd) i 2 c bus control signal no. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 item high level input voltage low level input voltage high level input current low level input current low level output voltage sda (pin 1) during 3 ma inflow max. inflow current input capacitance max. clock frequency minimum waiting time for data change minimum waiting time for start of data transfer low level clock pulse width high level clock pulse width minimum waiting time for start preparation min. data hold time min. data preparation time rise time fall time minimum waiting time for stop preparation symbol v ih v il i ih i il v ol i ol c i f scl t buf t hd:sta t low t high t su:sta t hd:dat t su:dat t r t f t su:sto min. 3.0 0 0 3 0 4.7 4.0 4.7 4.0 4.7 0 250 4.7 typ. max. 5.0 1.5 10 10 0.4 10 100 1 300 unit v ? v ma pf khz ? ns ? ns ? sda scl tbuf p s thd;sta tlow thd;dat thigh tr tf thd;sta tsu;sta sr tsu;sto p tsu;dat
?3 CXA1734S electrical characteristics measurement circuit nc lout rout itime vcatc vcawgt veout vetc vewgt ve sapout gnd noisetc vcain sapin sda scl dgnd sad vgr iref mainin plint stfil compin saptc subout stin v cc mainout 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a i 2 c bus data dgnd r1 220 r2 220 c3 10 r4 62k metal 1% c6 4.7 c8 1 c10 0.47 r6 2.2k c11 0.22 c13 4.7 c18 4.7 c17 4.7 signal generator gnd ac v cc v1 9v gnd c19 100 c16 4.7 c15 4.7 r8 3.3k 2700p c14 r7 3k 0.047 c12 tantalum 3.3 c9 c7 4.7 1 c5 10 r3 43k metal 1% c2 4.7 r5 3.9k c1 4.7 s4 s3 s2 s1 buff filters measures 15khz lpf f h bpf c4 200k r9 v2 tantalum
?4 CXA1734S i 2 c bus register data standard setting values classification a: adjustment u: user control s: proper to set t: test register att stvco sapvco saplpf stlpf spectral wideband test-da test1 nrsw fomo m1 sapc attsw number of bits 4 6 4 4 6 6 6 1 1 1 1 1 1 1 classification a a a a a a a t t u u u s s standard setting 9 1f 8 8 1f 1f 1f 0 0 1 contents center point normal mode according to the mode control table mute off fixed by the set specifications setting value when electrical characteristics are measured adjustment point list of adjustment contents 1 2 3 4 5 6 adjustment item main vca st vco sap vco st & dbx filter sap filter low frequency st separation high frequency st separation adjustment data att stvco sapvco stlpf saplpf wideband spectral input pin compin (pin 11) none compin (pin 11) compin (pin 11) compin (pin 11) compin (pin 11) compin (pin 11) input signal 100hz 245mvrms none 5f h (78.67k) 147mvrms 9.4khz 600mvrms 88khz 120mvrms st-l 30% 300hz st-l 30% 3khz measurement item lout output level rout output frequency sta7 (sapvco1) sta8 (sapvco2) sta3 (stlpf) sta4 (saplpf) rout output level rout output level adjustment contents adjust as close to 490 mvrms as possible adjust as close to 62.936 khz as possible adjust to the center of the sapvco1 = 0, sapvco2 = 1 condition adjust to the center of the stlpf = 1 condition adjust to the center of the saplpf = 1 condition minimize the output level minimize the output level test mode setting test-da=1 test1=1 test1=1
?5 CXA1734S adjustment method 1 att adjustment 1. test bit is set to ?est1 = 0?and ?est-da = 0? 2. input a 100 hz, 245 mvrms sine wave signal to compin and monitor the lout output level. then, adjust the ?tt?data for att adjustment so that lout output goes to the standard value. 3. adjustment range: ?0% adjustment bits: 4 bits 2 stereo vco adjustment 1. test bit is set to ?est1 = 0?and ?est-da = 1? 2. monitor the rout output (4 f h free run) frequency in a no input state, and adjust ?tvco?adjustment data so that this frequency is as close to 4f h (62.936 khz) as possible. 3. adjustment range: ?0% adjustment bits: 6 bits 3 sapvco adjustment 1. test bit is set to ?est1 = 0?and ?est-da = 0? 2. input a 5f h (sap carrier , 78.67 khz) , 147 mvrms sine wave signal to compin. while monitoring the status flag (sta7, sta8) condition, adjust ?apvco?adjustment data. 3. adjustment range: ?0% adjustment bits: 4 bits align sapvco with the center of the sta7 = 0 and sta8 = 1 (adjustment ok) condition range. 4 stereo block dbx filter adjustment 1. test bit is set to ?est1 = 1?and ?est-da = 0? 2. input a 9.4 khz, 600 mvrms sine wave signal to compin. while monitoring the status flag (sta3) condition, adjust the ?tlpf?adjustment data. 3. adjustment range: ?0% adjustment bits: 6 bits align stlpf with the center of the sta3 = 1 (adjustment ok) condition range. adjustment point 1 0 0f 1 0 control data "sapvco" measurement data sta7 "sapvco1" sta8 "sapvco2" adjustment point 0 3f 1 0 control data "stlpf" measurement data sta3 "stlpf"
?6 CXA1734S 5 sap block filter adjustment 1. test bit is set to ?est1 = 1?and ?est-da = 0? 2. input a 88 khz, 120 mvrms sine wave signal to compin. while monitoring the status flag (sta4) condition, vary and adjust the ?aplpf?adjustment data. 3. adjustment range: ?0% adjustment bits: 4 bits align saplpf with the center of the sta4 = 1 (adjustment ok) condition range. 6 separation adjustment 1. test bit is set to ?est1 = 0?and ?est-da = 0? 2. set the unit to stereo mode and input the left channel only signal (modulation factor 30%, frequency 300 hz) to compin. at this time, adjust the ?ideband?adjustment data to reduce rout output to the minimum. 3. next, set the frequency only of the input signal to 3 khz and adjust the ?pectral?adjustment data to reduce rout output to the minimum. 4. then, the adjustments in 2 and 3 above are performed to optimize the separation. 5. ?ideband ?pectral adjustment range: ?0% adjustment range: ?5% adjustment bits: 6 bits adjustment bits: 6 bits adjustment point 1 0 0f control data "saplpf" measurement data sta4 "saplpf"
?7 CXA1734S description of operation the us audio multiplexing system possesses the base band spectrum shown in fig. 1. fig. 1. base band spectrum fig. 2. overall block diagram (see fig. 3 for the dbx-tv block) fig. 3. dbx-tv block peak dev khz 50 25 25 l+r 50-15khz l-r dbx-tv nr 50 am-dsb-sc sap dbx-tv nr fm 10khz 50-10khz telemetry fm 3khz 15 f h =15.734khz f h 2f h 3f h 4f h 5f h 6f h 6.5f h f 5 pilot 3 29 28 7 8 14 19 11 13 a b (compin) stereo lpf pll (vco 8f h ) i 2 c bus decoder mode control pilot det mvca pilot cancel main lpf de.em (main out) l+r 4.7 (main in) l-r (dsb) det inj. lock subvca sub lpf wideband (subout) (st in) 4.7 nr sw dbx-tv block matrix (l-out) (r-out) mode control (sap in) 4.7 sap(fm) det sap lpf sap det sap bpf 18 (sap out) l-r i 2 c bus decoder mode control noise det i 2 c bus decoder 2f hl 0 f hl 90 f hl 0 14 19 23 24 a b nr sw fixed deemphasis variable deemphasis (ve out) (vca in) to matrix 4.7 hpf lpf lpf vca rms det rms det
?8 CXA1734S (1) l + r (main) after the audio multiplexing signal input from compin (pin 11) passes through mvca, the sap signal and telemetry signal are suppressed by stereo lpf. next, the pilot signals are canceled. finally, the l - r signal and sap signal are removed by main lpf, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2) l - r (sub) the l - r signal follows the same course as l + r before the pilot signal is canceled. l - r has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (dsb-am modulated). for this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the l - r signal. in the last stage, the residual high frequency components are removed by sub lpf and the l - r signal is input to the dbx-tv block via the nrsw circuit after passing through subvca. (3) sap sap is an fm signal using 5f h as a carrier as shown in the fig.1. first, the sap signal only is extracted using sap bpf. then, this is subjected to fm detection. finally, residual high frequency components are removed and freqency characteristics flattened using sap lpf, and the sap signal is input to the dbx-tv block via the nrsw circuit. when there is no sap signal, the pin 18 output is soft muted. (4) mode discrimination stereo discrimination is performed by detecting the pilot signal amplitude. sap discrimination is performed by detecting the 5f h carrier amplitude. noise discrimination is performed by detecting the noise near 25 khz after fm detection. (5) dbx-tv block either the sap signal or l - r signal input respectively from st in (pin 14) or sap in (pin 19) is selected by the mode control and input to the dbx-tv block. the input signal then passes through the fixed de-emphasis circuit and is applied to the variable de- emphasis circuit. the signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to vca (voltage control amplifier). finally, the vca output is converted from a current to a voltage using an operational amplifier and then input to the matrix. the variable de-emphasis circuit transmittance and vca gain are respectively controlled by each of effective value detection circuits. each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6) others ?vca?is a vca which adjusts the input signal level to the standard level of this ic. in addition, the input signal enters the decoder without passing through mvca by setting to attsw = 1. the signals (l + r, l - r, sap) input to ?atrix?are selected according to the bus data and whether there is st or sap discrimination, and any one of the st-l, st-r, mono or sap signals is output to lout and rout. ?ias?supplies the reference voltage and reference current to the other blocks. the currents flowing to the resistors connecting iref (pin 6) and itime (pin 27) with gnd become the reference current.
?9 CXA1734S register specifications slave address register table * : don't care status register when test1 = 0 when test1 = 1 sta1 sta2 sta3 sta4 sta5 sta6 sta7 sta8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 power stereo sap noise sap vco1 sap vco2 on reset sta1 sta2 sta3 sta4 sta5 sta6 sta7 sta8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 power stereo stlpf saplpf on reset sad pin slave receiver slave transmitter gnd 80h 81h v cc 8ah 8bh sub address msb lsb **** 0000 **** 0001 **** 0010 **** 0011 **** 0100 **** 0101 **** 0110 data bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 * attsw test-da test1 att [4] input level adj * stvco [6] stereo vco adj (sapvco [4] sap vco adj) (saplpf [4] sap filter adj) * stlpf [6] st filter adj * spectral [6] * wideband [6] * nrsw fomo sapc m1
?0 CXA1734S description of registers control registers * classification u: user control a: adjustment s: proper to set t: test status registers register att stvco sapvco saplpf stlpf spectral wideband test-da test1 nrsw fomo m1 sapc attsw number of bits 4 6 4 4 6 6 6 1 1 1 1 1 1 1 classifi- cation * a a a a a a a t t u u u s s contents input level adjustment stereo vco free running frequency adjustment sap vco free running frequency adjustment sap filter adjustment stereo and dbx filter adjustment adjustment of stereo separation (3 khz) adjustment of stereo separation (300 hz) turn to dac test mode and stvco adjustment mode by means of test-da = 1. turn to test mode by means of test = 1. (adjustment of stlpf and saplpf) selection of the output signal (stereo mode , sap mode) turn to forced mono by means of fomo = 1. (lout only is mono during sap output.) selection of mute on/off (0: mute on, 1: mute off) selection of sap mode or l + r mode according to the presence of sap broadcasting turns the input stage mvca off when attsw = 1. register ponres stereo sap noise stlpf saplpf sapvco1 sapvco2 number of bits 1 1 1 1 1 1 1 1 contents power on reset detection; 1: reset stereo discrimination of the input signal; 1: stereo sap discrimination of the input signal; 1: sap noise level discrimination of the input signal mode; 1: noise status of stereo filter adjustment; 1: ok range status of sap filter adjustment; 1: ok range status 1 of sap vco free running frequency adjustment; 0: ok range status 2 of sap vco free running frequency adjustment; 1: ok range
?1 CXA1734S description of control registers att (4): adjust the signal level input to compin (pin 11) to the reference level (245 mvrms). variable range of the input signal: 245 mvrms ?.0 db to +3.0 db 0 = level min. f = level max. stvco (6): adjust stereo vco free running frequency (f 0 ). variable range: f 0 ?0% 0 = free running frequency min. 3f = free running frequency max. sapvco (4): adjust sapvco free running frequency (f 0 ). variable range: f 0 ?0% 0 = free running frequency min. f = free running frequency max. saplpf (4): adjust the filter f 0 of the sap block. variable range: f 0 ?0% 0 = frequency min. f = frequency max. stlpf (6): adjust the filter f 0 of the st and dbx blocks. variable range: f 0 ?0% 0 = frequency min. 3f = frequency max. spectral (6): perform high frequency (fs = 3 khz) separation adjustment. 0 = level max. 3f = level min. wideband (6): perform low frequency (fs = 300 hz) separation adjustment. 0 = level min. 3f = level max. test1 (1): set filter adjustment mode. 0 = normal mode 1 = stlpf (sta3) and saplpf (sta4) adjustment mode in addition, the following outputs are present at pins 28 and 29. lout (pin 29): sap bpf out rout (pin 28): nr bpf out test-da (1): set dac output test mode and stvco adjustment mode. 0 = normal mode 1 = dac output test mode and stvco adjustment mode lout (pin 29): da control dc level rout (pin 28): stereo vco oscillation frequency (4 f h )
?2 CXA1734S nrsw (1) select stereo mode or sap mode 0 = stereo mode 1 = sap mode fomo (1): select forced mono mode 0 = normal mode 1 = forced mono mode sapc (1): select the sap signal output mode when there is no sap signal, the conditions for selecting sap output are selected by sapc. 0 = l + r output is selected 1 = sap output is selected attsw (1) main vca switch 0 = normal mode 1 = main vca is passed. m1 (1) mute the lout and rout output 0 = mute on 1 = mute off
?3 CXA1734S description of mode control priority ranking: test-da > test1 > m1 > (nrsw & fomo & sapc) mode control nrsw fomo sapc m1 test1 test-da sapc=0 ?elect dbx input and lout & rout output conditions: fomo = 0 nrsw = 0 (mono or st output) during st input: lout : l, rout : r during other input: lout : l + r, rout : l + r nrsw = 1 (sap output) when there is ?ap?during sap discrimination lout: sap, rout: sap ?when there is ?o sap? output is the same as when nrsw = 0. ?orced mono fomo = 1 during sap output: lout: l + r, rout: sap during st or mono output: lout: l + r, rout: l + r change the selection conditions for ?ono or st output?and ?ap output? sapc = 0: switch to sap output when there is sap discrimination. do not switch to sap output when there is no sap discrimination. sapc = 1: switch to sap output regardless of whether there is sap discrimination. ?ute m1 = 0 output is muted. ?est1 test1 = 1 return adjustment data with status register as an adjustment mode. in addition, outputs are as follows. lout: sap bpf out rout: nr bpf out ?est-da test-da = 1 used to test of d/a. lout: d/a output rout: stvco oscillation frequency (4 f h ) sapc=1 ?elect dbx input and lout & rout output conditions: fomo = 0 nrsw = 0 (mono or st output) as on the left nrsw = 1 (sap output) regardless of the presence of sap discrimination, dbx input: ?ap lout: sap, rout: sap however, when there is no sap, saplpf output is soft muted (? db)
?4 CXA1734S mode control no. 1 (sapc = 1) note) (sap) : the sapout output signal is soft muted (approximately ? db). the signal is soft muted when noise = 1. * : don? care. 1) : sap or noise discrimination may be made during mono or stereo input when the noise is inputted in the weak electric field. "noise" status rises earlier than "sap" status when the amount of noise is increased to compin. input signal mode mode detection mode control dbx output st sap noise nrsw fomo sapc input lch rch 0000 * 1 mute l+r l+r 000101sapsapsap mono 1) 000111sapl+rsap 0 * 10 * 1 mute l+r l+r 0 * 1101 (sap) (sap) (sap) 0 * 1111 (sap) l+r (sap) 10 * 001l-rlr 10 * 0 1 1 mute l+r l+r 111001l-rlr stereo 1) 111011 mute l+r l+r 100101sapsapsap 100111sapl+rsap 1 * 1101 (sap) (sap) (sap) 1 * 1111 (sap) l+r (sap) 01 * 0 0 1 mute l+r l+r 01 * 0 1 1 mute l+r l+r mono & sap 010101sapsapsap 010111sapl+rsap 011101 (sap) (sap) (sap) 011111 (sap) l+r (sap) 11 * 001l-rlr 11 * 0 1 1 mute l+r l+r stereo & sap 110101sapsapsap 110111sapl+rsap 111101 (sap) (sap) (sap) 111111 (sap) l+r (sap)
?5 CXA1734S mode control no. 2 (sapc = 0) note) (sap) : the sapout output signal is soft muted (approximately ? db). the signal is soft muted when noise = 1. * : don? care. 1) : sap or noise discrimination may be made during mono or stereo input when the noise is inputted in the weak electric field. "noise" status rises earlier than "sap" status when the amount of noise is increased to compin. input signal mode mode detection mode control dbx output st sap noise nrsw fomo sapc input lch rch 00 *** 0 mute l+r l+r mono 1) 011000 mute l+r l+r 011010 mute l+r l+r 011100 (sap) (sap) (sap) 011110 (sap) l+r (sap) 10 * 000l-rlr 10 * 0 1 0 mute l+r l+r 10 * 100l-rlr stereo 1) 10 * 1 1 0 mute l+r l+r 111000l-rlr 111010 mute l+r l+r 111100 (sap) (sap) (sap) 111110 (sap) l+r (sap) 010000 mute l+r l+r 010010 mute l+r l+r 010100sapsapsap mono & sap 010110sapl+rsap 011000 mute l+r l+r 011010 mute l+r l+r 011100 mute l+r l+r 011110 mute l+r l+r 110000l-rlr 110010 mute l+r l+r 110100sapsapsap stereo & sap 110110sapl+rsap 111000l-rlr 111010 mute l+r l+r 111100l-rlr 111110 mute l+r l+r
ack ack data data p 891 89 hiz hiz data(n) data(n+1) ack 189189 ack data(n+2) hiz hiz lsb msb s address 1 2 34 5 6789 1 8 9 sda scl msb l during write msb lsb hiz hiz ack sub address ack sda scl start condition s stop condition p h l hiz l ?6 CXA1734S i 2 c bus signal there are two i 2 c signals, sda (serial data) and scl (serial clock) signal. sda is a bidirectional signal. accordingly there are 3 values outputs, h, l and hiz. ? 2 c transfer begins with start condition and ends with stop condition. ?i 2 c data write (write from i2c controller to the ic) * data can be transferred in 8-bit units to be set as required. sub address is incremented automatically.
?7 CXA1734S ? 2 c data read (read from the ic to i 2 c controller) read timing * data read is performed during scl rise. s address 167891 89 scl ack data ack sda h during read hiz 7 p data 12345678 9 9 msb lsb ack ack ic output sda scl read timing
?8 CXA1734S input level vs. distortion characteristics 2 (stereo) input level vs. distortion characteristics 1 (mono) 1.0 0.1 ?0 0 10 input level [db] standard level (100%) input signal: mono (pre-emphasis on), 1 khz 0db=100% modulation lpf v cc =9v, 30khz using lpf measurement point: l/r out distortion (%) 10 1.0 ?0 0 10 input level [db] standard level (100%) input signal: stereo l=-r (dbx-tvnr on), 1khz 0db=100% modulation level v cc =9v, 30khz using lpf, st mode measurement point: l/r out input level vs. distortion characteristics 3 (sap) 10 1.0 ?0 0 10 input level [db] standard level (100%) input signal: sap (dbx-tvnr on) 1khz, 0db=100% modulation level v cc =9v, 30khz using lpf, sap mode measurement: l/r out distortion (%) distortion (%)
?9 CXA1734S frequency (khz) gain (db) stereo lpf frequency characteristics 10 5 0 ? ?0 0 20406080100 30 10 0 ?0 ?0 12 5 102050 7 70 100 ?0 ?0 ?0 20 main lpf and sub lpf frequency characteristics gain (fc main and fc sub) (db) 10 0 ?0 20 40 60 80 100 120 ?0 20 sap frequency characteristics and group delay gain (db) group delay 100 90 80 70 60 50 40 10 20 0 30 5f h gain group delay 3.8f h 6.2f h frequency (khz) frequency (khz)
?0 CXA1734S sony code eiaj code jedec code 30pin sdip (plastic) 26.9 ?0.1 + 0.4 15 16 30 1.778 10.16 8.5 ?0.1 + 0.3 0.25 ?0.05 + 0.1 0?to 15 0.5 0.1 0.9 0.15 3.0 min 0.5 min 3.7 ?0.1 + 0.4 sdip-30p-01 sdip030-p-0400 1 package structure molding compound lead treatment lead material package weight epoxy / phenol resin plating copper alloy 1.8g solder/palladium package outline unit : mm

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